diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 1c4370b..d0a7341 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -149,7 +149,7 @@
 	/* these memory control registers are set up in the assember part,
 	 * in sc520_asm.S, during 'mem_init'.  If we muck with them here,
 	 * after we are running a stack in RAM, we have troubles.  Besides,
-	 * these refresh and delay values are better ? simply specified 
+	 * these refresh and delay values are better ? simply specified
 	 * outright in the include/configs/{cfg} file since the HW designer
 	 * simply dictates it.
 	 */
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index e1fa37a..8fc713d 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -462,7 +462,7 @@
 
 #if defined CFG_SDRAM_DRCTMCTL
 	/* just have your hardware desinger _GIVE_ you what you need here! */
-	movl    $DRCTMCTL, %edi   
+	movl    $DRCTMCTL, %edi
 	movb    $CFG_SDRAM_DRCTMCTL,%al
 	movb    (%edi), %al
 #else
@@ -477,7 +477,7 @@
 #ifdef CFG_SDRAM_CAS_LATENCY_3T
 	orb     $0x10, %al
 #endif
-	movb    %al, (%edi) 
+	movb    %al, (%edi)
 #endif
 #endif
 	movl    $DRCCTL, %edi            /* DRAM Control register */
@@ -537,7 +537,7 @@
 	movl	%eax, %ebx
 
 
-done:	
+done:
 	movl	%ebx, %eax
 
 #if CFG_SDRAM_ECC_ENABLE
@@ -547,7 +547,7 @@
 	movl	$0x1, %edi
 memtest0:
 	movb	$0xa5, (%edi)
-	cmpb    $0xa5, (%edi) 
+	cmpb    $0xa5, (%edi)
 	jne	out
 	shrl	$1, %ecx
 	andl	%ecx,%ecx
@@ -571,11 +571,11 @@
 			/* enable NMI mapping for ECC */
 	movl    $ECCINT, %edi
 	mov	$0x10, %al
-	movb    %al, (%edi) 
+	movb    %al, (%edi)
 			/* Turn on ECC */
 	movl    $ECCCTL, %edi
 	mov	$0x05, %al
-	movb    %al, (%edi) 
+	movb    %al, (%edi)
 #endif
 out:
 	movl	%ebx, %eax